Method for producing a semiconductor component with electrical connection terminals for high integration density

ABSTRACT

A semiconductor component, wherein the common power supply is fed via buried metal layers (7, 9) which are present over the entire area and are connected to active functional elements (1) by vertical conductive connections (13, 15), the planes with which contact is not intended to be made being insulated from these vertical connections (13, 15) by dielectric (11) sheathing the latter.

SUMMARY OF THE INVENTION

The present invention relates to semiconductor components having aspecial structure for electrical connection which allows a highintegration density of functional elements on a chip.

For complex CMOS circuits, a positive supply voltage and a negativesupply voltage (VDD and VSS) must be fed in, and a multiplicity ofsignal lines must be routed between the individual transistors. For thispurpose, a plurality of wiring planes, i.e. layer-type portions havinginterconnections and metallizations, must be used, which contain, forexample, aluminum interconnections which are insulated from one anotherby a dielectric such as, for example, SiO2. Connections between theseindividual planes of interconnections and contacts or from the bottomplane to the transistors and other functional elements on the chip areproduced by metal contacts. These contacts are essentially metal-filledholes in the dielectric. With increasing circuit complexity, anever-increasing number of independent planes with interconnections isnecessary in order to provide the requisite electrical connections insufficient density. As the number of planes increases, the requirementfor planarity of the respective dielectric intermediate layersincreases, since if the individual layers are insufficiently planarized,production of the next interconnection plane gives rise to technologicaldifficulties. The minimum achievable dimensions of the individualstructures consequently increase drastically toward the upper planes.The so-called packing density that can be achieved is therebyconsiderably reduced. Small capacitances between the signal lines arefurthermore necessary for high operating speeds. Supply lines to theexternal electrical connection terminal should have the lowest possibleinput line resistances and a high current-carrying capacity. In thiscase, high capacitances are more beneficial, since these capacitancesact as charge stores and can block current spikes.

BACKGROUND OF THE INVENTION

The object of the present invention is to specify a design for asemiconductor component, in which the complexity of the electricalconnections is reduced for large-scale integration of the functionalelements.

In general terms the present invention is a method for producing asemiconductor component having at least one buried full-area metal layerwhich is provided with a connection terminal for external power supply,and having active functional elements in a silicon layer. In a firststep, a layer structure consisting of each buried full-area metal areaand this silicon layer for these active functional elements is producedon a substrate. Dielectric layers for electrical insulation are in eachcase applied between these layers. In a second step, these activefunctional elements are produced. In a third step, openings which ineach case extend such that a region, intended for making contact, of afunctional element is exposed in each opening. In a fourth step, adielectric is applied onto the wall of these openings up to a heightprovided for electrical insulation. This region provided for makingcontact remains exposed in each case. In a fifth step, these openingsare filled with metal in order to produce vertical electricallyconductive connections between the respective metal layer and thisregion, provided for making contact, of the functional element.

Advantageous developments of the present invention are as follows.

The fourth step is carried out by depositing the dielectric into theopenings, etching away the dielectric anisotropically outside and on thebottom of the openings, filling the openings with a material thatresists the etching, in each case up to the height up to which thedielectric is intended to remain, removing the portion of dielectricthereby remaining exposed and removing the material that resists thisetching.

In the first step, each buried full-area metal layer is produced from asilicide of a metal from the group titanium, tungsten and tantalum.

The first step is carried out by, in a first additional step, applyingat least one full-area metal layer onto a first substrate and coveringit with a full-area dielectric layer and applying a dielectric layerover the whole area onto a second silicon substrate. In a secondadditional step, these dielectric layers are brought to face each otherand are connected together by wafer bonding.

The semiconductor component is produced in the framework of a CMOSprocess. In the first step, two such metal layers are produced, whichare each provided with a connection terminal for the positive pole orthe negative pole, respectively, of a supply voltage.

The semiconductor component according to the invention reduces thecomplexity of the electrical connections by virtue of the fact thatfull-area metal layers are present for input of the external supplyvoltage. These metal layers are buried in the substrate or between thesubstrate and the active semiconductor layers and are insulated from oneanother by dielectric intermediate layers. The semiconductor componentaccording to the invention can be produced particularly advantageouslywith CMOS circuits using SOI (silicon on insulator) technology. Thesignal lines are in this case arranged conventionally over thefunctional elements, i.e. on the side remote from the substrate. Thesignal lines are produced in the form of conventional interconnectionsand metal contacts. It is possible for only one full-area buried metallayer, for example as the ground connection contact, or at least twometal layers, each for one of the supply voltages VDD and VSS, to bepresent. Connection of the functional elements (transistors and thelike) to these metal layers is produced by vertical conductiveconnections through the dielectric intermediate layers. Theseconnections are, for example, thin vertically arranged metal pins ormetal cylinders which are laterally enclosed all round by the dielectricof the intermediate layers. Instead of this, it is also possible forlarger apertures to be etched in the layer planes and for the verticalconnections to be produced by interconnections which do not completelyfill these openings. However, in view of the desired planar design ofthe semiconductor component, a buried form of contact between metallayers and interconnections, which are respectively arranged in oneplane of the layer structure, is expedient. When a plurality offull-area metal planes for the supply voltage are present, theconnection terminals of the active functional elements in the layerstructure are connected to the full-area metal planes arranged furtheraway using vertically arranged conductors which are routed throughapertures in the full-area metal planes arranged in between and areinsulated from the latter by dielectric sheathing.

This semiconductor component design according to the invention has theadvantage that a complete metal layer is in each case used for feedingin each pole of a supply voltage. Microstructuring is therefore notrequired for this input line. The production outlay is thereby reducedand leads to a higher expected yield of operational components.Unstructured conductor planes need not be planarized with dielectriclayers. The unstructured metal planes promote the dissipation of heatlosses during operation of the active functional elements. Thecapacitance between a plurality of full-area metal layers acts as abuffer for current spikes occurring in the supply current. Thus, adimension of 50 nm for the insulation oxide between the metal layersresults in a capacitance of approximately 70 nF per cm2 of chip surfacearea. The input line resistance can be minimized since the metal layersprovided for the supply voltage are unstructured and their thickness isnot limited by microstructuring or subsequent planarization. There maybe as many such full-area buried metal layers as desired for connectionof supply voltages. For the positive connection terminal and thenegative connection terminal, two metal layers, which are separated fromeach other by an insulating intermediate layer, are expediently arrangedparallel one above the other.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several figures of which like referencenumerals identify like elements, and in which:

FIG. 1 depicts a first step of the present invention in which a layeredstructure is formed;

FIG. 2 depicts a second step of the present invention in which activecomponents are produced;

FIG. 3 depicts the etching of opening or apertures according to thepresent invention;

FIG. 4 depicts the step of filling the aperture with metal according tothe present invention; and

FIG. 5 depicts deposition of a dielectric layer over the entire area.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown in FIG. 1, a first dielectric layer 6, a metal layer 7, asecond dielectric layer as the intermediate layer 8, a further metallayer 9 and a third dielectric layer 10 are applied one above the otherover the whole area onto a substrate 12 (for example of silicon). Adielectric layer 2 (for example oxide) is applied over the whole areaonto a further substrate 1 (for example likewise silicon). The twocoated substrates 1, 12 are connected together by wafer bonding via thetop layers, i.e. the oxide layer 2 on the substrate 1 and the thirddielectric layer 10 on the substrate 12. The three dielectric layers 6,8, 10 on the first substrate 12 can likewise be, for example, oxide. Themetal layers 7, 9 are, for example, high-melting metals such astitanium, tungsten, tantalum or silicides of these metals, or copper,gold or an aluminum alloy. The oxide layers 2, 10, which are connectedtogether by wafer bonding, form the insulator layer of the SOI substrateproduced in this way. The top substrate wafer in FIG. 1 is then thinned,for example by means of chemical mechanical polishing, to a thickness ofat most 100 nm, if the intention is to produce exclusivelydepletion-mode MOSFETs. For other active components such as, forexample, bipolar transistors, the residual thickness of this siliconlayer remaining should be matched accordingly. As represented in FIG. 2,active components, in this example exclusively depletion-mode CMOStransistors, are then produced in the thinned silicon layer 1.

These transistors are produced in the silicon layer 1. Insulationregions 3 are produced between the active regions. This is done, forexample, by structuring the silicon layer 1 and filling the insulationregions with oxide, or by local oxidation of these portions of thesilicon layer. The active regions are doped by ion implantation to setthe threshold voltage for the transistors. The dielectric (for examplethermal oxide RTP) of the gate is produced and the gate material (forexample doped polysilicon or metal or metal silicide) is deposited andstructured. The gate contact 4 is marked on FIG. 2. The diffusionregions for the source and the drain are doped by means of ionimplantation and subsequent activation (annealing). A dielectric layer 5is deposited as a passivation layer over the whole area.

The vertical conductive connections to the metal layers 7, 9 aresubsequently produced. Using a mask (photolithography), the material isetched in a cylindrical opening as far as the upper metal layer 9. Thematerial of the dielectric layers is etched and, if appropriate,material of the silicon layer 1 is etched selectively with respectthereto. A contact hole for the lower metal layer 7 is correspondinglyetched through the upper metal layer 9. In order to insulateelectrically from other conductor planes the vertical conductiveconnections to be produced, dielectric 11 (for example oxide, PECVD) isdeposited into the etched apertures. This dielectric 11 isanisotropically etched away outside and on the bottom of the etchedaperture (see FIG. 3). The dielectric 11 is removed in the upper part sothat the connection terminal, with which contact is to be made, of thetransistor is exposed. For this purpose, the aperture is filled, with amaterial, for example resist, that resists the etching, up to a heightto which the dielectric is intended to remain, and the exposed portionof the dielectric is then etched away anisotropically in the upperregion. The regions with which contact is to be made are then exposed.The aperture can then be filled with metal 13 (see FIG. 4) bydepositing, for example, tungsten over the whole area using CVD andetching it back on the upper side. The dielectric 11 insulates thismetal, which forms the vertical conductive connection 13, from theplanes with which contact is not to be made.

A dielectric layer 14 is then deposited over the whole area andplanarized (for example oxide deposited using CVD) (see FIG. 5). Usingphotolithography, apertures are produced in this dielectric layer 14above the metallic connections 13 produced. These apertures are, asdescribed above, filled with the metal of the vertical connections. Byagain using photolithography, it is then possible to produce on theplanarized surface of the dielectric layer 14 metal contacts 16 on theupper ends of the vertical conductive connections 13, 15 extended asdescribed. These contacts are structured in the conventional manner. Theabove-described procedural steps can be repeated correspondingly to makecontact with additional metal planes or for connection of the metallayers 7, 9 to conductive-track planes arranged above. In intermediatesteps, respectively planarizing dielectric layers are then applied asintermediate layers for the metallization planes. The arrangement canthen, if appropriate, be passivated using a cover layer. FIG. 5 showsthe finished structure in cross section. The connection terminals forthe external power supply are produced by corresponding etching of thelayers burying the metal layers 7, 9. It is sufficient, for example, toetch away completely the layers present on a respective metal layer in alateral region of the component that is not provided with functionalelements, in order to expose the relevant metal layer. The bottom metallayer 7 can, for example, be exposed through the substrate 12. Theburied full-area metal layers can also be produced by growing a layerstructure on a substrate. The described production using wafer bondingis particularly simple and advantageous in view of the knowntechnologies. The structure of the vertical conductive connections can,according to requirements, be matched to the specific component.Production is simplified by virtue of the fact that the verticalconductors can be produced, in the procedural steps for producing thehorizontal interconnections, starting from the upper side of thecomponent. The number of metal planes in the exemplary embodiment inFIG. 4 is not restricted to two; it is possible, for example, for thereto be only a single full-area buried metal layer present, or a pluralitythereof, which are in each case insulated from one another by dielectricintermediate layers. When making contact with metal layers respectivelylocated at greater depths, the vertical connection should in each casebe insulated from the metal planes arranged above by a dielectricsheathing.

The invention is not limited to the particular details of the methoddepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described method withoutdeparting from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted.

What is claimed is:
 1. A method for producing a semiconductor component having at least one buried full-area metal layer which is provided with a connection terminal for an external power supply, and having active functional elements in a silicon layer, comprising the steps of:in a first step, producing a layer structure having at least one buried full-area metal layer and having said silicon layer for the active functional elements, on a substrate; and applying dielectric layers for electrical insulation between said layers; in a second step producing said, active functional elements; in a third step, etching openings which extend as far as one of said metal layers such that a region, intended for making contact, of a functional element is exposed in each opening; in a fourth step, applying a dielectric onto a wall of said openings up to a height provided for electrical insulation, said region for making contact remaining exposed in each opening; in a fifth step, said openings are filled with metal to produce vertical electrically conductive connections between the respective metal layer and said region, provided for making contact, of the functional element.
 2. The method as claimed in claim 1, wherein the fourth step is carried out by depositing the dielectric into the openings, etching away the dielectric anisotropically outside of and on the bottom of the openings, filling the openings with a material that resists the etching, in each opening up to a height to which the dielectric is intended to remain, removing a portion of the dielectric remaining exposed and removing material that resists this etching.
 3. The method as claimed in claim 1, wherein, in the first step, each buried full-area metal layer is produced from a silicide of a metal from the group titanium, tungsten and tantalum.
 4. The method for producing a semiconductor component as claimed in claim 1, wherein the first step is carried out by, in a first additional step, applying at least one full-area metal layer onto a first substrate and covering it with a full-area dielectric layer and applying a further dielectric layer over the whole area onto a second silicon substrate and, in a second additional step, bringing said full-area dielectric layer and said further dielectric layer to face each other and connecting them together by wafer bonding.
 5. The method as claimed in claim 1 wherein the semiconductor component is produced in the framework of a CMOS process, and wherein, in the first step, two such metal layers are produced, which are each provided with a connection terminal for a positive pole or a negative pole of a supply voltage. 